Semiconductor memory device and address conversion circuit

ABSTRACT

It is an object of the present invention to provide a semiconductor memory device with a suitable redundancy circuit and an address conversion circuit, wherein external addresses are allocated to both a memory cell array which needs refresh, typically DRAM and another memory cell array which does not need refresh, typically SRAM. The semiconductor memory device comprises a dynamic memory cell array  11  further comprising an array of a plurality of dynamic memory cells, a static memory cell array  12  further comprising an array of a plurality of static memory cells, a pre-decoder  101  for converting an external address Add into a row pre-decode signal A 1  or A 2  which corresponds to any memory cell in the dynamic memory cell array  11  or the static memory cell array  12,  a redundancy program circuit  103  for specifying a memory cell being to be replaced in the dynamic memory cell array  11,  and a second conversion means (redundancy judging circuit) for converting an external address Add, which corresponds to the memory cell specified by the redundancy program circuit  103,  into a row pre-decode signal A 4,  which corresponds to a predetermined memory cell in the static memory cell array  12.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device and anaddress conversion circuit, and more particularly to a semiconductormemory device which has a memory cell array needing refresh typicallyDRAM (a dynamic random access memory) and another memory cell arrayneeding no refresh typically SRAM (a static random access memory), aswell as a redundancy circuit provided for remedying a specificdefecrtive part of a memory cell.

BACKGROUND OF ART

In conventional electronic devices such as portable terminals, there maybe two kinds of operation mode, for example, a normal operation modecausing a relatively large power consumption and a stand-by mode savinga power consumption. For example, a portable telephone device performscommunications and data input-output operations in the normal operationmode and queues for receiving in the stand-by mode. Such portabletelephone device is provided with a non-volatile memory such as a flashmemory and a volatile memory such as an SRAM and a DRAM, which are usedfor different purposes, taking into account different features ofperformances (or specification) of those memories. The non-volatilememory is used mainly for holding data for a long term. The SRAMexhibits a high speed access and has a low power consumption, for whichreason the SRAM is used for storing data which receive frequent accessesin the stand-by mode in addition to the normal mode. The DRAM needsrefresh operations and causes a relatively large power consumption buthas a large capacity, for which reason the DRAM is used mainly forproviding a data storing area in the normal mode. For example, data suchas telephone numbers are stored in the non-volatile memory, becausethose data are needed to be held even when a battery power is lost. Datastored in the SRAM are data which receive frequent accesses and areprevented from disappearing in a stand-by state, such as data used forcommunication to a base station in the stand-by state. A relativelylarge amount of data such as display data are stored in the DRAM becausethose data are allowed to be disappeared in the stand-by state.

Japanese laid-open patent publication No. 10-124200 “portableinformation terminal” describes one example of the conventionalconfigurations, wherein a normal operation mode and a stand-by mode (orsuspend mode) are provided for a portable information terminal includingSRAM and DRAM as described above. In accordance with the configurationdescribed in this publication, a high speed execution of a systemsoftware appears in the normal operation mode, while in the stand-bymode, the data area is switched from the DRAM to the SRAM, forsubsequent low speed execution of a power control program which has beenstored in a ROM (read only memory) and the SRAM. Examples of the controlmethods for having accesses to both the SRAM and the DRAM with the sameconfiguration are described in Japanese laid-open patent publication No.6-139371 “microcomputer”, and Japanese laid-open patent publication No.1-166147 “memory control circuit”. In accordance with the prior artdescribed in Japanese laid-open patent publication No. 6-139371, asignal processor has accesses to both the SRAM and the DRAM, wherein amemory, to which an access is intend to be made, is discriminated. If anaccess-object is the SRAM, then all bits of the address are outputtedone time. If the access-object is the DRAM, then row and columnaddresses are outputted with time-division. In accordance with theconfiguration described in Japanese laid-open patent publication No.1-166147, there are further provided a refresh counter which generates arefresh address for the RAM and an address switching circuit, so that amultiple address and a non-multiple address are switched depending onthe access-object, and further a refresh operation to the DRAM isautomatically executed.

There are other conventional semiconductor memory devices with both theSRAM and the DRAM, wherein the SRAM with a small capacity is combined tothe DRAM with a relatively large capacity, so that the SRAM is used as acache memory of the DRAM. In accordance with this configuration, dataread operations from the DRAM and data write operations into the DRAMare taken place through the SRAM which allows relatively high speedaccesses, resulting in high speed accesses being realized. In thisconfiguration, however, only an address space of the DRAM is recognizedfrom outside of the semiconductor memory device. Independent accuses toboth the SRAM and the DRAM are not possible as described in the abovepublications.

Meanwhile, the other conventional semiconductor memory device utilizes atechnique for saving a device function by replacing a defective bit lineor a defective word line with any defectiveness caused in themanufacturing processes, into a bit line or a word line in a redundancymemory cell array provided in the same semiconductor memory device. Theredundancy memory cell array may be provided in the same memory chip asthe memory cell array which should be saved, or in a redundancy chipwhich is provided over a mounting board and is separated from the memorycell array which should be saved, wherein the mounting board has aplurality of memory chips or a packaged chip. Japanese laid-open patentpublication No. 8-16486 “defect-saving LSI and memory device” describesone example of the conventional saving configuration for replacing thedefect caused in the DRAM chip in a module into a redundancy SRAM chipin the module.

DISCLOSURE OF INVENTION

It is an object of the present invention to provide a semiconductormemory device with a suitable redundancy circuit and an addressconversion circuit, wherein external addresses are allocated to both amemory cell array which needs refresh, typically DRAM and another memorycell array which does not need refresh, typically SRAM.

The present invention provides a semiconductor memory device comprising:a dynamic memory cell array further comprising an array of a pluralityof dynamic memory cells; a static memory cell array further comprisingan array of a plurality of static memory cells; a first conversion means(pre-decoder) for converting an external address into an address whichcorresponds to any memory cell in the dynamic memory cell array or thestatic memory cell array; a memory cell specifying means for specifyingat least a memory cell in the dynamic memory cell array, the at leastmemory cell being to be replaced; and a second conversion means(redundancy judging circuit) for converting an external address, whichcorresponds to the at least memory cell specified by the memory cellspecifying means, into an address, which corresponds to a predeterminedmemory cell in the static memory cell array.

The semiconductor memory device may further comprise: a refresh controlmeans for controlling refresh operations to the dynamic memory cellarray; and a control means for at least discontinuing operations therefresh control means based on an external control signal.

The refresh control means may further include: a refresh addressgenerating circuit for repeatedly generating a refresh address whichcorresponds to each memory cell of the dynamic memory cell array, basedon a predetermined timing signal; and a selecting circuit for selectingany one of the external address and the refresh address.

A supply of a power to the dynamic memory cell array may be discontinuedby the external control signal.

The memory cell specifying means may be adopted to specify a memory cellwhich is to be replaced in the dynamic memory cell array and alsospecifies another memory cell which is to be replaced in the staticmemory cell array.

The second conversion means may be adopted for converting an externaladdress, which corresponds to the at least memory cell specified by thememory cell specifying means, into an address, which corresponds to apredetermined memory cell in the static memory cell array. When thesecond conversion means converts the external address, which correspondsto the memory cell specified by the memory cell specifying means, intothe address, which corresponds to the predetermined memory cell in thestatic memory cell array, the second conversion means converts theexternal address into the address within the address range specified bythe memory cell specifying means, and also the second conversion meansconverts an external address, which corresponds to a memory cell otherthan the memory cells specified by the memory cell specifying means,into an address outside an address range set by an address range settingmeans.

The present invention further provides a semiconductor memory devicecomprising: a first memory cell array having a plurality of memory cellswhich need refresh; a second memory cell array having a plurality ofmemory cells which do not need refresh; and a first conversion circuitfor comparing a replaced address, which designates a memory cell to bereplaced in the first and second memory cell arrays, with an externalinput address, wherein if the replaced address does not correspond tothe external address, then the first conversion circuit allows an accessto a memory cell designated by the external address, and wherein if thereplaced address corresponds to the external address, then the firstconversion circuit converts the external address into areplace-destination address, with which the replaced address is to bereplaced, the replace-destination address designates a memory cell in apredetermined area in the second memory cell array, and the firstconversion circuit allows an access to the replace-destination address.

A replaced address memory circuit may further be provided for storingthe replaced address. The replaced address memory circuit may comprise aprogram circuit.

If the replaced address does not correspond to the external address,then the first address conversion circuit may generate a signal whichinvalidates a first address signal designating a memory cell in thefirst memory cell array, a second address signal designating a memorycell in the second memory cell array, and a selecting signal selectingany one of the first and second memory cell arrays.

A replace-destination address range setting circuit may further beprovided for setting a replace-destination address range in the secondmemory cell array, so that if the replaced address does not correspondto the external address, then the first address conversion circuitconverts the external address into an address outside thereplace-destination address range as set, and if the replaced addresscorresponds to the external address, then the first address conversioncircuit converts the external address into an address in thereplace-destination address range as set.

The first memory cell array may have a dedicated decode circuit fordecoding an address in the predetermined area, and the first addressconversion circuit may supply the replace-destination address directlyto the decode circuit.

The present invention further provides an address conversion circuit forconverting an address which designates a memory cell in a semiconductormemory device which has a first memory cell array having a plurality ofmemory cells which need refresh, and a second memory cell array having aplurality of memory cells which do not need refresh, wherein the addressconversion circuit compares a replaced address, which designates amemory cell to be replaced in the first and second memory cell arrays,with an external input address, wherein if the replaced address does notcorrespond to the external address, then the address conversion circuitallows an access to a memory cell designated by the external address,and wherein if the replaced address corresponds to the external address,then the address conversion circuit converts the external address into areplace-destination address, with which the replaced address is to bereplaced, the replace-destination address designates a memory cell in apredetermined area in the second memory cell array, and the firstconversion circuit allows an access to the replace-destination address.

A replaced address memory circuit may further be provided for storingthe replaced address. The replaced address memory circuit may comprise aprogram circuit.

If the replaced address does not correspond to the external address,then the address conversion circuit may generate a signal whichinvalidates a first address signal designating a memory cell in thefirst memory cell array, a second address signal designating a memorycell in the second memory cell array, and a selecting signal selectingany one of the first and second memory cell arrays.

The first memory cell array may have a dedicated decode circuit fordecoding an address in the predetermined area, and the addressconversion circuit supplies the replace-destination address directly tothe decode circuit.

BRIEF DESCRIPTION OF DRAWING

FIG. 1 is a block diagram illustrative of a configuration of asemiconductor memory device of a first embodiment in accordance with thepresent invention.

FIG. 2 is a block diagram illustrative of a configuration of asemiconductor memory device of a second embodiment in accordance withthe present invention.

FIG. 3 is a block diagram illustrative of a configuration of asemiconductor memory device of a third embodiment in accordance with thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment

A first embodiment of the semiconductor memory device in accordance withthe present invention will hereinafter be described with reference tothe drawing. FIG. 1 is a block diagram illustrative of a configurationof a semiconductor memory device of a first embodiment in accordancewith the present invention. The semiconductor memory device shown inFIG. 1 comprises a DRAM cell array 11, which further comprises aplurality of DRAM memory cells, an SRAM cell array 12, which furthercomprises a plurality of SRAM memory cells, and peripheral circuitsthereof, which are provided on a single chip. The block diagram of FIG.1 is to illustrate a primary configuration of the feature of the presentinvention, while illustration of the same configurations as the priorart are partly omitted.

An external address Add is a signal comprising plural bits whichrepresent an address which designates a memory cell, to which an accessis to be made, in the DRAM cell array 11 or the SRAM cell array 12. Theexternal address Add is supplied from an external control circuit (notillustrated) such as a CPU (central processing unit) through an addressbus. In this case, the external address Add may be the same type asnormally used in the SRAM, namely all bits thereof are concurrentlysupplied. Notwithstanding, similarly to the normal DRAM, row bits andcolumn bits may be supplied in the form of time-division, wherein aninternal configuration of an input unit for receiving the externaladdress Add is adopted, for example, an internal configuration of apre-decoder 101 may be adopted.

A chip select signal CS is an external signal which designates anoperational mode of the semiconductor memory device. In this case, ifthe chip select signal CS is active, then the normal operation mode isselected. If the chip select signal CS is inactive, then the stand-bymode is selected. The normal operation mode is to allow data read andwrite operations from and to each memory cell of the DRAM cell array 11and the SRAM cell array 12.

In the normal operation mode, refresh operations to the DRAM cell array11 are automatically executed at a predetermined time interval. In thestand-by mode, the refresh operations to the DRAM cell array 11 arediscontinued. Accordingly, in the stand-by mode, data in the SRAM cellarray 12 are held, while data in the DRAM cell array 11 are not held.

The pre-decoder 101 fetches the external address Add at thepredetermined timing and judges whether the external address Add isallocated to the DRAM cell array 11 or the SRAM cell array 12. If theexternal address Add designates an address of the DRAM cell array 11,then the pre-decoder 101 decodes the external address Add to a rowpre-decode signal A1 and a column pre-decode signal A3, and outputs thelow and column pre-decode signals A1 and A3, as well as outputs acell-selecting signal C1 which shows that an access is to be made to theDRAM cell array 11. If the external address Add designates an address ofthe DRAM cell array 11, then the pre-decoder 101 decodes the externaladdress Add to a row pre-decode signal A2 and the column pre-decodesignal A3, and outputs the low and column pre-decode signals. A1 and A3,as well as outputs a cell-selecting signal C1 which shows that an accessis to be made to the SRAM cell array 12. The SRAM cell array 12 ispreviously divided in the row address unit into a data storage region 12a and a redundancy region 12 b. The row pre-decode signal A2 outputtedfrom the pre-decoder 101 corresponds to the data storage region 12 a.

A redundancy judging circuit 102 is a circuit for judging whether therow address included in the external address Add corresponds to any ofzero to plural address values designated by a redundancy program circuit103. Namely, the redundancy judging circuit 102 is a circuit for judgingwhether a memory cell (a word line) in the DRAM cell array 11 or theSRAM cell array 12, which corresponds to the external address Add, wouldbe the memory cell (the word line) which is needed to be saved (orreplaced) by the redundancy memory cell. The zero to plural addressvalues designated by the redundancy program circuit 103 represent a rowaddress of a memory cell which is not usable as being defective in theDRAM cell array 11 and the SRAM cell array 12. If the redundancy judgingcircuit 102 confirmed that the row address included in the externaladdress Add corresponds to any of the address values designated by theredundancy program circuit 103, then the redundancy judging circuit 102outputs a row pre-decode signal A4 which has been obtained bypre-decoding a row address pre-determined for every address designatedby the redundancy program circuit 10, wherein the row address is in theredundancy region 12 b of the SRAM cell array 12. This row pre-decodesignal A4 is a selecting signal which corresponds to a row address, towhich a replacement is to be made, or a row address in the redundancyregion 12 b.

The redundancy judging circuit 102 outputs a killer signal C2 whichrenders valid or invalid (null) the row pre-decode signals A1 and A2outputted from the pre-decoder 101. In this embodiment, if the killersignal C2 is high level “H”, then the row pre-decode signals A1 and A2are valid. If the killer signal C2 is low level “L”, then the rowpre-decode signals A1 and A2 are invalid (null).

Accordingly, if the redundancy judging circuit 102 judged that the rowaddress included in the external address Add corresponds to any of theaddress values designated by the redundancy program circuit 103, thenthe redundancy judging circuit 102 outputs the killer signal C2 of lowlevel “L” to render the row pre-decode signals A1 and A2 invalid (null),and also render the cell-selecting signal C1 invalid (null), therebyforcing to select the SRAM cell array 12. Further, the redundancyjudging circuit 102 places an output line of the row pre-decode signalA4 into a low impedance state.

If the redundancy judging circuit 102 judged that the row addressincluded in the external address Add does not correspond to any addressvalues designated by the redundancy program circuit 103, then theredundancy judging circuit 102 outputs the killer signal C2 of highlevel “H” to render the row pre-decode signals A1 and A2 valid, and alsorender the cell-selecting signal C1 valid, thereby to select either theDRAM cell array 11 or the SRAM cell array 12 in accordance with thecell-selecting signal C1. Further, the redundancy judging circuit 102places the output line of the row pre-decode signal A4 into a highimpedance state.

In this embodiment, a gate circuit 124 is provided to take anAND-operation of the cell-selecting signal C1 and the killer signal C2to supply the same to a column decoder 109. If the logic level outputtedfrom the gate circuit 124 is “L”, then the column decoder 109 forces toselect the SRAM cell array 12. If the logic level is “H”, then thecolumn decoder 109 forces to select the DRAM cell array 11 or the SRAMcell array 12 in accordance with the cell-selecting signal C1.

The redundancy program circuit 103 generates and outputs a signal whichrepresents a row address which corresponds to a word line, on which amemory cell is present, which is defective in a hold-characteristic or acharacteristic or an operation of transistor, in each memory cells inthe DRAM cell array 11 or in each memory cells in the data storageregion 12 a of the SRAM cell array 12. The redundancy program circuit103 may, for example, be configured by utilizing a non-volatile memory,interconnections which are disconnectable by a laser or an accesscurrent or fuse circuits. The address to be programmed is an address ofthe word line which includes a memory cell which has been judged to bedetective based on the result of tests for operations and performancesof the memory cells in the manufacturing test.

The row pre-decode signal A1 outputted from the pre-decoder 101 isinputted into the gate circuit 104 which has an input and an output forplural bits. If the killer signal C2 is high level, then the gatecircuit 104 allows the row pre-decode signal A1 to pass through. If thekiller signal C2 is low level, then the gate circuit 104 outputs a rowpre-decode signal of low level “L” which means that all bits arenon-selective state independent from the row pre-decode signal A1. Thesignal with the plural bits outputted from the gate circuit 104 isinputted into one input of a multiplexer 105 having input and output forplural bits.

A refresh address generating circuit 106 repeatedly generates a refreshaddress AS which corresponds to all row addresses of the DRAM cell array11, in accordance with a timing signal C3 supplied from a refreshcontrol circuit 107, and supplies the refresh address A5 to anotherinput of the multiplexer 105. A pre-decoder 116 pre-decodes the refreshaddress A5 and outputs a row pre-decode signal A11. A refresh controlcircuit 107 is a circuit for controlling a timing of execution of therefresh operation to the DRAM cell array 11. The refresh control circuit107 controls a timing of generating refresh addresses based on a timingsignal C3 so that each memory cell in the DRAM cell array 11 isrefreshed at a time interval within a data holding time. The refreshcontrol circuit 107 also controls switching operations of themultiplexer 105 based on a switch signal C4. The refresh control circuit107 repeatedly generates the timing signal C3 at a predetermined timeinterval, and also generates the switching signal C4 at a refreshtiming, so that the multiplexer 105 selects the row pre-decode signalA11 in the refresh address A5. The multiplexer 105 selects any one ofthe row pre-decode signal A1 inputted through the gate circuit 104 basedon the switching signal C4 and the row pre-decode signal A11 and outputsthe same as a row pre-decode signal A6.

A chip select signal CS is inputted into the refresh address generatingcircuit 106, the refresh control circuit 107 and a power circuit 13. Thepower circuit 13 is a circuit for generating a boosted voltage, asubstrate voltage and a refresh voltage which are used for operating theDRAM cell array 11. Each of the refresh address generating circuit 106,the refresh control circuit 107 and the power circuit 13 is providedwith a circuit for allowing operation of the each circuit if the chipselect signal CS is active, and for discontinuing the operation if thechip select signal CS is inactive. An example of this circuit is aswitch for ON-OFF operation of the power line based on the chip selectsignal CS.

If a row enable signal outputted from a control circuit not illustratedis active, then the row decoder 108 decodes a row pre-decode. signal A6to activate a word line designated by a decoded result. If the killersignal C2 is low level “L” at a time when the row pre-decode signal A1is selected, then all bits of the row pre-decode signal A6 are low level“L”, whereby any word lines are not activated.

If the cell-selecting signal C1 designates the DRAM cell array 11, thena column decoder 109 decodes a column pre-decode signal A3 and generatesand outputs a column selecting signal A7 for selecting a bit line in theDRAM cell array 11 which is designated by the decoded result. If thecell-selecting signal C1 designates the SRAM cell array 12, then acolumn decoder 109 decodes the column pre-decode signal A3 and generatesand outputs a column selecting signal A8 for selecting a bit line in theSRAM cell array 12 which is designated by the decoded result.

A sense amplifier pre-charge circuit 110 for the DRAM cell array 11comprises sense amplifiers and column switches adopted to the DRAM cellarray 11 and a pre-charge circuit. The column switch connects a senseamplifier and a data bus WRB, wherein the sense amplifier has beendesignated by the column selecting signal A7 outputted from a columndecoder 109. If the sense amplifier enable signal is active, then thesense amplifier senses and amplifies a voltage of a bit line connectedto a memory cell connected to a word line selected by a row decoder 108,and supplies the amplified voltage to the data bus WRB, or supplieswrite data on the data bus WRB through a bit line to a memory cell,wherein the write data are stored in the memory cell. If the pre-chargeenable signal is active, then the pre-charge circuit pre-charges apotential of the bit line up to a predetermined voltage, for example, ½of a power voltage.

A sense amplifier pre-charge circuit 111 for the SRAM cell array 12comprises sense amplifiers and column switches adopted to the SRAM cellarray 12 and a pre-charge circuit. The column switch connects a senseamplifier and the data bus WRB, wherein the sense amplifier has beendesignated by the column selecting signal A8 outputted from the columndecoder 109. If the sense amplifier enable signal is active, then thesense amplifier senses and amplifies a voltage of a bit line connectedto a memory cell connected to a word line selected by a row decoder 112,and supplies the amplified voltage to the data bus WRB, or supplieswrite data on the data bus WRB through a bit line to a memory cell,wherein the write data are stored in the memory cell. If the pre-chargeenable signal is active, then the pre-charge circuit pre-charges bothpotentials of the paired bit lines up to the power voltage. The rowdecoder 112 decodes either one of the row pre-decode signal A2 suppliedthrough the gate circuit 113 and the row pre-decode signal A4 suppliedthrough the redundancy judging circuit 102, and activates a word linedesignated by the decode result. The gate circuit 113 has the sameconfiguration as the gate circuit 114.

The semiconductor memory device of FIG. 1 with the above configurationoperates as follows.

(1) if the chip select signal CS is low level “L”, then operations of abuffer circuit for data input-output are discontinued, whereby input andoutput of data through the data bus WRB are discontinued. Operations ofthe refresh address generating circuit 106, the refresh control circuit107 and the power circuit 13 are discontinued. After a predeterminedtime has passed, then all data in the DRAM cell array 11 are erased. Apower voltage is supplied to the SRAM cell array 12, whereby data in theSRAM cell array 12 are held.

(2a) in case that the chip select signal CS is high level “H”, if theexternal address Add has a value corresponding to a memory cell in theDRAM cell array 11 and if the redundancy judging circuit 102 judged thatthis memory cell is not needed to be saved or replaced, then the cellselecting signal C1 becomes a level which represents that an access isto be made to the DRAM cell array 11, and the killer signal C2 becomeshigh level “H”, whereby the pre-decoder 101 outputs the row pre-decodesignal A1 and the column pre-decode signal A3 based on the externaladdress Add. The column decoder 109 generates the column selectingsignal A7 based on the column pre-decode signal A3 and supplies the sameto the sense amplifier pre-charge circuit 110, resulting in that writeand read operations to a memory cell in the DRAM cell array 11 areexecuted based on the row pre-decode signal A1 and the column pre-decodesignal A3 decoded by the pre-decoder 101.

At a predetermined cycle, the row pre-decode signal A11 is supplied tothe row decoder 108, and the sense amplifier pre-charge circuit 110 iscontrolled by a control signal which is not illustrated, whereby memorycells in the DRAM cell array 11 are refreshed sequentially in the wordline unit. The refresh operations to the DRAM cell array 11 are executedsimilarly under other operational conditions (2b), (3a) and (3b),wherein the chip select signal CS is high level “H”.

(2b) in case that the chip select signal CS is high level “H”, if theexternal address Add has a value corresponding to a memory cell in theDRAM cell array 11 and if the redundancy judging circuit 102 judged thatthis memory cell is needed to be saved or replaced, then the cellselecting signal C1 becomes a level which represents that an access isto be made to the DRAM cell array 11, and the killer signal C2 becomeslow level “L”, whereby the pre-decoder 101 outputs the row pre-decodesignal A1 and the column pre-decode signal A3 based on the externaladdress Add. Since the killer signal C2 is low level “L”, a selectsignal with all bits of low level “L” as the row pre-decode signal A6 issupplied to the row decoder 108, whereby word lines in the DRAM cellarray 11 are not activated. Since the killer signal C2 is low level “L”,the column decoder 109 generates the column selecting signal A8 based onthe column pre-decode signal A3 and supplies the column selecting signalA8 to the sense amplifier pre-charge circuit 111. The row pre-decodesignal A4 is supplied to the row decoder 112. Write and read operationsto a memory cell connected to a predetermined word line in the SRAM cellarray 12 are executed based on the row pre-decode signal A4 and thecolumn pre-decode signal A3 outputted from the redundancy judgingcircuit 102.

(3a) in case that the chip select signal CS is high level “H”, if theexternal address Add has a value corresponding to a memory cell in theSRAM cell array 12 and if the redundancy judging circuit 102 judged thatthis memory cell is not needed to be saved or replaced, then the cellselecting signal C1 becomes a level which represents that an access isto be made to the SRAM cell array 12, and the killer signal C2 becomeshigh level “H”, whereby the pre-decoder 101 outputs the row pre-decodesignal A2 and the column pre-decode signal A3 based on the externaladdress Add. The column decoder 109 generates the column selectingsignal A8 based on the column pre-decode signal A3 and supplies the sameto the sense amplifier pre-charge circuit 111, resulting in that writeand read operations to a memory cell in the region 12 a of the SRAM cellarray 12 are executed based on the row pre-decode signal A2 and thecolumn pre-decode signal A3 decoded by the pre-decoder 101.

(3b) in case that the chip select signal CS is high level “H”, if theexternal address Add has a value corresponding to a memory cell in theSRAM cell array 12 and if the redundancy judging circuit 102 judged thatthis memory cell is needed to be saved or replaced, then the cellselecting signal C1 becomes a level which represents that an access isto be made to the SRAM cell array 12, and the killer signal C2 becomeslow level “L”, whereby the pre-decoder 101 outputs the row pre-decodesignal A2 and the column pre-decode signal A3 based on the externaladdress Add. Since the killer signal C2 is low level “L”, the columndecoder 109 generates the column selecting signal A8 based on the columnpre-decode signal A3 and supplies the column selecting signal A8 to thesense amplifier pre-charge circuit 111. The row pre-decode signal A4 issupplied to the row decoder 112. Write and read operations to a memorycell connected to a predetermined word line in the redundancy region 12b of the SRAM cell array 12 are executed based on the row pre-decodesignal A4 and the column pre-decode signal A3 outputted from theredundancy judging circuit 102.

As described above, in accordance with this embodiment, a memory cell tobe saved in the DRAM cell array 11 and the SRAM cell array 12 is savedor replaced by a memory cell in the predetermined redundancy region inthe SRAM cell array 12. In contrast to this embodiment, if a redundancymemory cell for the DRAM cell array 11 is provided as the other DRAMcell, it is necessary to provide a refresh circuit and a control circuitfor the DRAM cell serving as the redundancy memory cell. In accordancewith this embodiment, the SRAM cell, which does not need refresh, servesas a redundancy cell for the DRAM cell array 11, thereby allowingreductions in circuit configuration and circuit scale. Further, inaccordance with the present invention, redundancy memory cells for theSRAM cells and other redundancy memory cells for the DRAM cells areprovided in the same region and commonly use a circuit for accessthereto. This allows a further simplification of the circuit.

Second Embodiment

A second embodiment will hereinafter be described with reference to FIG.2. The semiconductor memory device shown in FIG. 2 has two row decoders112 a and 112 b instead of the row decoder 112. In the configurationshown in FIG. 2, the same constitutional elements as in FIG. 1 areprovided with the same reference numbers or codes. The row-decoder 112 adecodes a row pre-decode signal A9 of the gate circuit 113 to activateany word line in the region 12 a of the SRAM cell array 12. Therow-decoder 112 b decodes a row pre-decode signal A4 outputted from theredundancy judging circuit 102 to activate any word line in the region12 b of the SRAM cell array 12.

In accordance with this embodiment, in addition: to the effects obtainedin the first embodiment, the following effects are obtained. dedicateddecoders respectively for the regions 12 a and 12 b in the SRAM cellarray 12, so that the bit number of the row pre-decode signal A4 may belimited to the corresponding number to the word line number in theregion 12 b.

Third Embodiment

A third embodiment will hereinafter be described with reference to FIG.3. The semiconductor memory device shown in FIG. 3 has an area switchingcircuit 114 and an area program circuit 115, and further a configurationin a redundancy program circuit 103 a for processing signals from thearea program circuit 115, in addition to the configuration of FIG. 1. Inthe configuration shown in FIG. 3, the same constitutional elements asin FIG. 1 are provided with the same reference numbers or codes.

The area switching circuit 114 and the area program circuit 115 areprovided in order to allow optionally setting or allocating a datastorage area 12 a and a redundancy area 12 b in the SRAM cell array 112.For example, it is possible that the entirety of the SRAM cell array 112may be configured to be divided into a plurality of divided areas basedon word lines, for example, 16 divided areas, wherein fourteen dividedareas constitute the data storage area 12 a and the remaining twodivided areas constitute the redundancy area 12 b. The area programcircuit 115 outputs data, based on which the redundancy area 12 b (orthe data storage area 12 a) is defined. The area switching circuit 114converts the row pre-decode signal A2 into a row pre-decode signal A10which corresponds to the data storage area 12 a and also converts therow pre-decode signal A4 into a row pre-decode signal A10 whichcorresponds to the redundancy area 12 b. The area program circuit 115comprises a fuse circuit which includes programmable interconnectionsand active elements by a laser irradiation or an excess currentapplication in the fabrication process. The area program circuit 115outputs data which represent the number of the divided areas inaccordance with the program statement, (for example, the number is anoptional from 0˜16). The area switching circuit 114 may also comprise aplurality of multiplexer circuits, and gate circuits for renderinginvalid (null) the row pre-decode signal A2 upon supply of the rowpre-decode signal A4. The redundancy program circuit 103 a decides anaddress, at which a replacement is to be made, based on signals from thearea program circuit 115, wherein the signals represent states of theredundancy area 12 b and he data storage area 12 a.

In accordance with this embodiment, in addition to the effects obtainedin the first embodiment, the following effects are obtained. Since, forexample, the placement and capacity of the redundancy area 12 b mayoptionally be set for each memory chip, then the redundancy area 12 bmay be set in an area free of any defective cell, and it is alsopossible to optionally change the ratio of the area 12 a to the area 12b.

The embodiments of the semiconductor memory device in accordance withthe present invention have been described with reference to FIGS. 1–3.Notwithstanding, the embodiments are not intended to limit the presentinvention. Design changes are available for integrating circuit blocksand dividing each circuit functions and adding conventional otherconfigurations. In the above embodiment, the external access is madesimilarly to the SRAM, wherein the normal address Add isnon-synchronously supplied in parallel to all bits. Notwithstanding, itis possible that similarly to the normal DRAM, the column address andthe row address are supplied in time-division, or similarly to the SRAM(synchronous DRAM), the normal address is supplied in synchronizing witha clock signal. In the embodiments, the refresh control circuit for DRAMis provided in the semiconductor memory device. The refresh controlcircuit may be provided outside the semiconductor memory device. In theembodiment, the redundancy memory cell is provided for the word lineunit. The redundancy memory cell may be provided for the bit line unitor the plural word line unit. It is not essential that all of therespective constitutional elements of the semiconductor memory deviceare provided in a single memory chip. It is possible to use a pluralityof memory chips to form a memory module.

Further, in the first to third embodiments, the DRAM cell array is theexample of the memory cell array which needs refresh, while the SRAMcell array is the example of the memory cell array which does not needrefresh. The present invention is not intended to limit this example.The present invention is applicable to other examples that the memorycell array, which does not need refresh, may comprise non-volatilememory cell array such as a Flash cell array, an FeRAM cell array, anMRAM cell array, and an EEPROM cell array.

Further, an entirety of the circuit of the semiconductor memory devicecomprising the memory cell arrays and peripheral circuits may be mountedon a single chip or may be divided into plural function blocks which aremounted on plural chips respectively and separately. In the later case,it is possible that the memory cell array and the peripheral circuit areprovided on chips separately to form a hybrid IC. It is also possiblethat in the peripheral circuit, only redundancy circuits such as theredundancy program circuit 103, the area switching circuit 114 and thearea program circuit are provided on the other chip than the memory chipto form another hybrid IC.

Whereas the embodiments of the present invention have been describedabove, the present invention is not intended to limit those embodiments.Design changes without deviation from the subject matters of the presentinvention are included in the present invention.

INDUSTRIAL APPLICABILITY

In accordance with this invention, the following effects are obtained.There are provided a dynamic memory cell array further comprising anarray of a plurality of dynamic memory cells; a static memory cell arrayfurther comprising an array of a plurality of static memory cells; afirst conversion means for converting an external address into anaddress which corresponds to any memory cell in said dynamic memory cellarray or said static memory cell array; a memory cell specifying meansfor specifying at least a memory cell in said dynamic memory cell array,said at least memory cell being to be replaced; and a second conversionmeans for converting an external address, which corresponds to said atleast memory cell specified by said memory cell specifying means, intoan address, which corresponds to a predetermined memory cell in saidstatic memory cell array. The redundancy memory cells comprise SRAMcells, and any refresh circuit for refreshing the redundancy memorycells is unnecessary, thereby reducing the scales of the redundancymemory and the peripheral circuit in the semiconductor memory device,wherein the external addresses are allocated to both the DRAM and theSRAM.

1. A semiconductor memory device, comprising: a dynamic memory cellarray further comprising an array of a plurality of dynamic memorycells; a static memory cell array further comprising an array of aplurality of static memory cells; a first conversion means forconverting an external address into an address which corresponds to anymemory cell in said dynamic memory cell array or said static memory cellarray; a memory cell specifying means for specifying at least one memorycell in said dynamic memory cell array, said at least one memory cellbeing to be replaced; and a second conversion means for converting anexternal address, which corresponds to said at least one memory cellspecified by said memory cell specifying means, into an address, whichcorresponds to a predetermined memory cell in said static memory cellarray, wherein said memory cell specifying means specifies a memory cellwhich is to be replaced in said dynamic memory cell array and alsospecifies another memory cell which is to be replaced in said staticmemory cell array.
 2. The semiconductor memory device as claimed inclaim 1, further comprising: a refresh control means for controllingrefresh operations to said dynamic memory cell array; and a controlmeans for at least discontinuing operations said refresh control meansbased on an external control signal.
 3. The semiconductor memory deviceas claimed in claim 1, further comprising: a refresh address generatingcircuit for repeatedly generating a refresh address which corresponds toeach memory cell of said dynamic memory cell array, based on apredetermined timing signal; and a selecting circuit for selecting anyone of said external address and said refresh address.
 4. Thesemiconductor memory device as claimed in claim 1, wherein a supply of apower to said dynamic memory cell array is discontinued by an externalcontrol signal.
 5. The semiconductor memory device as claimed in claim1, wherein when said second conversion means converts said externaladdress, which corresponds to said memory cell specified by said memorycell specifying means, into said address, which corresponds to thepredetermined memory cell in said static memory cell array, said secondconversion means converts said external address into said address withinsaid address range specified by said memory cell specifying means, andalso said second conversion means converts an external address, whichcorresponds to a memory cell other than said memory cells specified bysaid memory cell specifying means, into an address outside an addressrange set by an address range setting means.
 6. A semiconductor memorydevice comprising: a first memory cell array having a plurality ofmemory cells which need refresh; a second memory cell array having aplurality of memory cells which do not need refresh; and a firstconversion circuit for comparing a replaced address, which designates amemory cell to be replaced in said first and second memory cell arrays,with an external input address, wherein if said replaced address doesnot correspond to said external address, then said first conversioncircuit allows an access to a memory cell designated by said externaladdress, and wherein if said replaced address corresponds to saidexternal address, then said first conversion circuit converts saidexternal address into a replace-destination address, with which saidreplaced address is to be replaced, said replace-destination addressdesignates a memory cell in a predetermined area in said second memorycell array, and said first conversion circuit allows an access to saidreplace-destination address.
 7. The semiconductor memory device asclaimed in claim 6, further including: a replaced address memory circuitfor storing said replaced address.
 8. The semiconductor memory device asclaimed in claim 7, wherein said replaced address memory circuitcomprises a program circuit.
 9. The semiconductor memory device asclaimed in claim 6, wherein if said replaced address does not correspondto said external address, then said first address conversion circuitgenerates a signal which invalidates a first address signal designatinga memory cell in said first memory cell array, a second address signaldesignating a memory cell in said second memory cell array, and aselecting signal selecting any one of said first and second memory cellarrays.
 10. The semiconductor memory device as claimed in claim 6,further including: a replace-destination address range setting circuitfor setting a replace-destination address range in said second memorycell array, wherein if said replaced address does not correspond to saidexternal address, then said first address conversion circuit convertssaid external address into an address outside said replace-destinationaddress range as set, and if said replaced address corresponds to saidexternal address, then said first address conversion circuit convertssaid external address into an address in said replace-destinationaddress range as set.
 11. The semiconductor memory device as claimed inclaim 6, wherein said first memory cell array has a dedicated decodecircuit for decoding an address in said predetermined area, and saidfirst address conversion circuit supplies said replace-destinationaddress directly to said decode circuit.
 12. An address conversioncircuit for converting an address which designates a memory cell in asemiconductor memory device which has a first memory cell array having aplurality of memory cells which need refresh, and a second memory cellarray having a plurality of memory cells which do not need refresh,wherein said address conversion circuit compares a replaced address,which designates a memory cell to be replaced in said first and secondmemory cell arrays, with an external input address, wherein if saidreplaced address does not correspond to said external address, then saidaddress conversion circuit allows an access to a memory cell designatedby said external address, and wherein if said replaced addresscorresponds to said external address, then said address conversioncircuit converts said external address into a replace-destinationaddress, with which said replaced address is to be replaced, saidreplace-destination address designates a memory cell in a predeterminedarea in said second memory cell array, and said first conversion circuitallows an access to said replace-destination address.
 13. The addressconversion circuit as claimed in claim 12, further including: a replacedaddress memory circuit for storing said replaced address.
 14. Theaddress conversion circuit as claimed in claim 13, wherein said replacedaddress memory circuit comprises a program circuit.
 15. The addressconversion circuit as claimed in claim 12, wherein if said replacedaddress does not correspond to said external address, then said addressconversion circuit generates a signal which invalidates a first addresssignal designating a memory cell in said first memory cell array, asecond address signal designating a memory cell in said second memorycell array, and a selecting signal selecting any one of said first andsecond memory cell arrays.
 16. The address conversion circuit as claimedin claim 12, wherein said first memory cell array has a dedicated decodecircuit for decoding an address in said predetermined area, and saidaddress conversion circuit supplies said replace-destination addressdirectly to said decode circuit.